The most important efforts of a Senior Logic Design Verification Engineer will be put to:
Compiling requirement oriented test plans, based on a solid understanding of a project logic design.
Developing of UVM environments, integrating of UVCs & developing coverage backed tests.
Testing by coverage driven environments, including stress/performance testing.
Finding bugs, debugging & finding root-cause in designs, implementing work-arounds in designs, to overcome schedule road-blocks.
Driving coverage metrics, according to an agreed work-plan, while finding trade-offs between remaining tasks & due dates.
Reporting status, communicating successes and challenges to a team leader on a weekly basis.
Key Qualifications
1. Graduate in Computer, Electrical or Software Engineering
2. Proven, hands-on, experience in logic design verification of 8 years
3. Proven, hands-on, experience with SystemVerilog UVM of 4 years
4. Experience working for projects in an international company of 2 years
5. Proven, hands-on, experience in defining & developing SystemVerilog Coverage
6. Experience in developing System Verilog Assertion (aka SVA)
7. Solid scripting skills in one of the following scripting languages: Python, Perl, TCL or BASH
8. Solid user experience in working on Linux based systems
9. Solid user experience in working with one of Version Control Systems: CVS, SVN, GIT,
Perforce, ClearCase, Mercury
10. Hands-on experience with image-processing designs in defence industry - advantage
11. Hands-on experience with FPGA design development - advantage
12. Experience with GIT version control system - advantage
13. Firmware programming experience in C - advantage
14. DevOps experience - advantage
General
The position offers a senior role in developing products for the defence market, mainly in the field of Image Processing. You'll work closely with Logic Design Engineers, reviewing & helping to define testable specifications. You are expected to provide on-going support of a test-harness. You'll have opportunities to carry out a full cycle of Logic Design Verification project life. The cycle will start from compiling requirement oriented test-plans and run via time-bound working plan to lab- integration and then to hitting coverage milestones. You'll have opportunities to development environments from scratch by using advanced UVM boiler-plate automation to speed up the initial curve & setup, maintain CI on different levels. You'll be responsible for completing tasks according to a work-plan commitments & raise flags, if reprioritizing is required. Metrics for your success will be bug-count, in-time smooth lab-integration & coverage completeness.
